Verilogの最初の一歩

入力を反転

module Lesson1(switch, led);
  input switch;
  output led;

  assign led = !switch;

endmodule // 

テストベンチ

module tb_Lesson1;

reg in;
wire out;

Lesson1 l1 (in, out);

initial begin
$dumpfile("Lesson1.vcd");
$dumpvars(0, tb_Lesson1);
$monitor ("%t: in = %b, out = %b", $time, in, out);

in = 0;
#10 in = 1;
#5 in = 0;
#15 in = 1;
#1 in = 0;
#2 in = 1;
#10 $finish;
end

endmodule