HaskellでFPGAの最小のサンプル

入力を反転するだけのコード

Not gate

コンパイル

$ stack exec -- clash --interactive
CLaSHi, version 0.99 (using clash-lib, version 0.99):
http://www.clash-lang.org/  :? for help
Clash.Prelude> :cd ../worka
Clash.Prelude> :! ls
Clash01.hs
Clash.Prelude> :l Clash01.hs
[1 of 1] Compiling Clash01          ( Clash01.hs, interpreted )
Ok, modules loaded: Clash01.
*Clash01>

Verilog生成

*Clash01> :verilog
Loading dependencies took 2.500923s
Compiling: Clash01.topEntity
Applied 64 transformations
Normalisation took 1.056631s
Netlist generation took 0.006391s
Compiling: Clash01.testBench
Applied 219 transformations
Testbench normalisation took 0.550645s
Testbench netlist generation took 0.030401s
Total compilation took 4.170923s
*Clash01> :! ls
Clash01.dyn_hi  Clash01.dyn_o   Clash01.hi  Clash01.hs  Clash01.o   verilog
*Clash01> :! tree
.
├── Clash01.dyn_hi
├── Clash01.dyn_o
├── Clash01.hi
├── Clash01.hs
├── Clash01.o
└── verilog
    └── Clash01
        ├── Clash01_testBench
        │   ├── Clash01_outputVerifier.v
        │   ├── Clash01_stimuliGenerator.v
        │   └── Clash01_testBench.v
        ├── Clash01_testBench.vcd
        ├── Clash01_topEntity.manifest
        ├── Clash01_topEntity.v
        └── main.exe

3 directories, 12 files
*Clash01>

波形ファイルを作るためにテストベンチを修正

A Testbench

波形ファイル生成

$ find . -name "*.v" | xargs iverilog -o main.exe
$ ./main.exe
VCD info: dumpfile Clash01_testBench.vcd opened for output.

波形ファイルの確認